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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 2000 mos integrated circuit pd160903 384/402-output tft-lcd source driver (compatible with 64-gray scales) data sheet document no. s14578ej1v1ds00 (1st edition) date published june 2001 ns cp (k) printed in japan the mark shows major revised points. description the pd160903 is a source driver for tft-lcds capable of dealing with displays with 64-gray scales. data input is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 262,144 colors by output of 64 values -corrected by an internal d/a converter and 5-by-2 external power modules. because the output dynamic range is as large as v ss2 + 0.1 v to v dd2 ? 0.1 v, level inversion operation of the lcd?s common electrode is rendered unnecessary. also, to be able to deal with dot-line inversion, n-line inversion and column line inversion when mounted on a single side, this source driver is equipped with a built-in 6-bit d/a converter circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. assuring a clock frequency of 45 mhz when driving at 2.7 v. features ? cmos level input ? 384/402 outputs ? input of 6 bits (gray-scale data) by 6 dots ? capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a d/a converter ? logic power supply voltage (v dd1 ): 2.7 to 3.6 v ? driver power supply voltage (v dd2 ): 5.5 v 0.275 v ? high-speed data transfer: f clk = 45 mhz (internal data transfer speed when operating at v dd1 = 2.7 v) ? output dynamic range: v ss2 + 0.1 v to v dd2 ? 0.1 v ? apply for dot-line inversion, n-line inversion and column line inversion ? output voltage polarity inversion function (pol) ? display data inversion function (pol21, pol22) ? single-side mounting is possible (incorporation of slim tcp) ordering information part number package pd160903n-xxx tcp (tab package) remark the tcp?s external shape is customized. to order the required shape, so please contact one of our sales representatives.
data sheet s14578ej1v1ds 2 pd160903 1. block diagram sthl v dd1 v ss1 v dd2 v ss2 s 2 s 1 v 0 to v 9 pol d 00 to d 05 c 1 c 2 c 66 c 67 stb clk 67-bit bidirectional shift register data register latch level shifter d/a converter voltage follower output r,/l sthr d 10 to d 15 d 20 to d 25 s 3 s 402 pol21, pol22 d 30 to d 35 d 40 to d 45 d 50 to d 55 test o sel remark /xxx indicates active low si gnal. 2. relationship between output circuit and d/a converter s 1 s 2 s 401 6-bit d/a converter s 402 v 4 5 5 pol multi- plexer v 9 v 0 v 5
data sheet s14578ej1v1ds 3 pd160903n-xxx) (copper foil surface, face-up) s 402 s 401 s 400 sthl s 399 d 55 d 54 d 53 d 52 d 51 d 50 d 45 d 44 d 43 d 42 d 41 d 40 d 35 d 34 d 33 d 32 d 31 d 30 v dd1 test r , /l v 9 v 8 v 7 v 6 v 5 v dd2 v ss2 v 4 v 3 v 2 v 1 v 0 o sel v ss1 clk stb pol pol21 pol22 d 25 d 24 d 23 d 22 d 21 d 20 d 15 d 14 d 13 d 12 d 11 d 10 d 05 d 04 d 03 s 4 d 02 s 3 d 01 s 2 d 00 s 1 sthr co pp er foil surface remark this figure does not specify the tcp package.
data sheet s14578ej1v1ds 4 (1/2) pin symbol pin name i/o description s 1 to s 402 driver output o the d/a converted 64-gray-scale analog voltage is output. o sel selection number of outputs switching io sel := h or open: 384 outputs (output pinss 193 through s 210 are invalid) o sel : = l: 402 outputs pulled up internally in the lsi. d 00 to d 05 d 10 to d 15 d 20 to d 25 d 30 to d 35 d 40 to d 45 d 50 to d 55 display data i the display data is input with a width of 36 bits, viz., the gray scale data (6 bits) by 6 dots (2 pixels). d x0 : lsb, d x5 : msb r,/l shift direction control i refers to the shift direction control. the shift directions of the shift registers are as follows. r,/l = h (right shift): sthr (input), s 1 s 402 , sthl (output) r,/l = l (left shift) : sthl (input), s 402 s 1 , sthr (output) sthr right shift start pulse i/o sthl left shift start pulse i/o these refer to the start pulse i/o pins when driver ics are connected in cascade. fetching of display data starts when h is read at the rising edge of clk. r,/l = h (right shift): sthr input, sthl output r,/l = l (left shift): sthl input, sthr output a high level should be input as the pulse of one cycle of the clock signal. if the start pulse input is more than 2clk, the first 1clk of the high-level input is valid. clk shift clock i refers to the shift register?s shift clock input. the display data is incorporated into the data register at the rising edge. at the rising edge of the 67th clock (64th clock in 384 outputs mode) after the start pulse input, the start pulse output reaches the high level, thus becoming the start pulse of the next-level driver. if 69th clock (66th clock in 384 mode) pulses are input after input of the start pulse, input of display data is halted automatically. the contents of the shift register are cleared at the stb?s rising edge. stb latch input the contents of the data register are transferred to the latch circuit at the rising edge. and, at the falling edge, the gray scale voltage is supplied to the driver after 4clk . it is necessary to ensure input of one pulse per horizontal period. pol polarity i pol = l: the s 2n?1 output uses v 0 to v 4 as the reference supply. the s 2n output uses v 5 to v 9 as the reference supply. pol = h: the s 2n?1 output uses v 5 to v 9 as the reference supply. the s 2n output uses v 0 to v 4 as the reference supply. s 2n-1 indicates the odd output: and s 2n indicates the even output. input of the pol signal is allowed the setup time (t pol - stb ) with respect to stb?s rising edge. pol21, pol22 data inversion i data inversion can invert when display data is loaded. pol21: invert/not invert of display data d 00 to d 05 , d 10 to d 15 , d 20 to d 25 . pol22: invert/not invert of display data d 30 to d 35 , d 40 to d 45 , d 50 to d 55 . pol21, pol22 = h : display data is inverted. pol21, pol22 = l : display data is not inverted. test test i normally, test = h or open. this pin is pulled up to the v dd1 power supply inside the ic v 0 to v 9 -corrected power supplies ? input the -corrected power supplies from outside by using operational amplifier. make sure to maintain the following relationships. during the gray scale voltage output, be sure to keep the gray scale level power supply at a constant level. v dd2 ? 0.1 v v 0 > v 1 > v 2 > v 3 > v 4 > 0.5 v dd2 > v 5 > v 6 > v 7 > v 8 > v 9 v ss2 + 0.1 v
data sheet s14578ej1v1ds 5 (2/2) pin symbol pin name i/o description v dd1 logic power supply ? 2.7 to 3.6 v v dd2 driver power supply ? 5.5 v 0.275 v v ss1 logic ground ? grounding v ss2 driver ground ? grounding cautions 1. the power start sequence must be v dd1 , logic input, and v dd2 & v 0 to v 9 in that order. reverse this sequence to shut. 2. to stabilize the supply voltage, please be sure to insert a 0.1 f bypass capacitor between v dd1 -v ss1 and v dd2 -v ss2 . furthermore, for increased precision of the d/a converter, insertion of a bypass capacitor of about 0.01 f is also recommended between the -corrected power supply terminals (v 0 , v 1 , v 2 ,....., v 9 ) and v ss2 .
data sheet s14578ej1v1ds 6 the pd160903 incorporates a 6-bit d/a converter whose odd output pins and even output pins output respectively gray scale voltages of differing polarity with respect to the lcd?s counter electrode voltage. the d/a converter consists of ladder resistors and switches. the ladder resistors (r0 to r62) are designed so that the ratio of lcd panel -compensated voltages to v 0 ? to v 63 ? and v 0 ? to v 63 ? is almost equivalent. for the 2 sets of five -compensated power supplies, v 0 to v 4 and v 5 to v 9 , respectively, input gray scale voltages of the same polarity with respect to the common voltage. figure 5?1 shows the relationship between the driving voltages such as liquid-crystal driving voltages v dd2 and v ss2 , common electrode potential v com , and -corrected voltages v 0 to v 9 and the input data. be sure to maintain the voltage relationships as follows: v dd2 ? 0.1 v v 0 > v 1 > v 2 > v 3 > v 4 > 0.5 v dd2 > v 5 > v 6 > v 7 > v 8 > v 9 v ss2 + 0.1 v figures 5?2 and 5?3 indicates the relationship between the input data and output voltage and the resistance values of the resistor strings. figure 5?1. relationship between input data and -corrected power supplies v dd2 v ss2 v 1 v 2 v 3 v 4 v com v 5 v 6 v 7 v 8 00 10 20 30 input data (hex) 3f 0.1 v v 9 0.1 v 16 16 16 16 16 16 15 15 v 0 0.5 v dd2 split interval
data sheet s14578ej1v1ds 7 v 0 > v 1 > v 2 > v 3 > v 4 > 0.5 v dd2 , pol21, pol22 = l data dx5 dx4 dx3 dx2 dx1 dx0 rn resitance ratio 00h 0 0 0 0 0 0 v0' v0 r0 800 01h 0 0 0 0 0 1 v1' v1+(v0-v1) 7250 / 8050 r1 750 02h 0 0 0 0 1 0 v2' v1+(v0-v1) 6500 / 8050 r2 700 03h 0 0 0 0 1 1 v3' v1+(v0-v1) 5800 / 8050 r3 650 04h 0 0 0 1 0 0 v4' v1+(v0-v1) 5150 / 8050 r4 600 05h 0 0 0 1 0 1 v5' v1+(v0-v1) 4550 / 8050 r5 550 06h 0 0 0 1 1 0 v6' v1+(v0-v1) 4000 / 8050 r6 550 07h 0 0 0 1 1 1 v7' v1+(v0-v1) 3450 / 8050 r7 500 08h 0 0 1 0 0 0 v8' v1+(v0-v1) 2950 / 8050 r8 500 09h 0 0 1 0 0 1 v9' v1+(v0-v1) 2450 / 8050 r9 400 0ah 0 0 1 0 1 0 v10' v1+(v0-v1) 2050 / 8050 r10 400 0bh 0 0 1 0 1 1 v11' v1+(v0-v1) 1650 / 8050 r11 350 0ch 0 0 1 1 0 0 v12' v1+(v0-v1) 1300 / 8050 r12 350 0dh 0 0 1 1 0 1 v13' v1+(v0-v1) 950 / 8050 r13 350 0eh 0 0 1 1 1 0 v14' v1+(v0-v1) 600 / 8050 r14 300 0fh 0 0 1 1 1 1 v15' v1+(v0-v1) 300 / 8050 r15 300 10h 0 1 0 0 0 0 v16' v1 r16 300 11h 0 1 0 0 0 1 v17 v2+(v1-v2) 2450 / 2750 r17 250 12h 0 1 0 0 1 0 v18' v2+(v1-v2) 2200 / 2750 r18 250 13h 0 1 0 0 1 1 v19' v2+(v1-v2) 1950 / 2750 r19 250 14h 0 1 0 1 0 0 v20' v2+(v1-v2) 1700 / 2750 r20 200 15h 0 1 0 1 0 1 v21' v2+(v1-v2) 1500 / 2750 r21 200 16h 0 1 0 1 1 0 v22' v2+(v1-v2) 1300 / 2750 r22 200 17h 0 1 0 1 1 1 v23' v2+(v1-v2) 1100 / 2750 r23 150 18h 0 1 1 0 0 0 v24' v2+(v1-v2) 950 / 2750 r24 150 19h 0 1 1 0 0 1 v25' v2+(v1-v2) 800 / 2750 r25 150 1ah 0 1 1 0 1 0 v26' v2+(v1-v2) 650 / 2750 r26 150 1bh 0 1 1 0 1 1 v27' v2+(v1-v2) 500 / 2750 r27 100 1ch 0 1 1 1 0 0 v28' v2+(v1-v2) 400 / 2750 r28 100 1dh 0 1 1 1 0 1 v29' v2+(v1-v2) 300 / 2750 r29 100 1eh 0 1 1 1 1 0 v30' v2+(v1-v2) 200 / 2750 r30 100 1fh 0 1 1 1 1 1 v31' v2+(v1-v2) 100 / 2750 r31 100 20h 1 0 0 0 0 0 v32' v2 r32 100 21h 1 0 0 0 0 1 v33' v3+(v2-v3) 1500 / 1600 r33 100 22h 1 0 0 0 1 0 v34' v3+(v2-v3) 1400 / 1600 r34 100 23h 1 0 0 0 1 1 v35' v3+(v2-v3) 1300 / 1600 r35 100 24h 1 0 0 1 0 0 v36' v3+(v2-v3) 1200 / 1600 r36 100 25h 1 0 0 1 0 1 v37' v3+(v2-v3) 1100 / 1600 r37 100 26h 1 0 0 1 1 0 v38' v3+(v2-v3) 1000 / 1600 r38 100 27h 1 0 0 1 1 1 v39' v3+(v2-v3) 900 / 1600 r39 100 28h 1 0 1 0 0 0 v40' v3+(v2-v3) 800 / 1600 r40 100 29h 1 0 1 0 0 1 v41' v3+(v2-v3) 700 / 1600 r41 100 2ah 1 0 1 0 1 0 v42' v3+(v2-v3) 600 / 1600 r42 100 2bh 1 0 1 0 1 1 v43' v3+(v2-v3) 500 / 1600 r43 100 2ch 1 0 1 1 0 0 v44' v3+(v2-v3) 400 / 1600 r44 100 2dh 1 0 1 1 0 1 v45' v3+(v2-v3) 300 / 1600 r45 100 2eh 1 0 1 1 1 0 v46' v3+(v2-v3) 200 / 1600 r46 100 2fh 1 0 1 1 1 1 v47' v3+(v2-v3) 100 / 1600 r47 100 30h 1 1 0 0 0 0 v48' v3 r48 100 31h 1 1 0 0 0 1 v49' v4+(v3-v4) 3350 / 3450 r49 100 32h 1 1 0 0 1 0 v50' v4+(v3-v4) 3250 / 3450 r50 100 33h 1 1 0 0 1 1 v51' v4+(v3-v4) 3150 / 3450 r51 100 34h 1 1 0 1 0 0 v52' v4+(v3-v4) 3050 / 3450 r52 100 35h 1 1 0 1 0 1 v53' v4+(v3-v4) 2950 / 3450 r53 150 36h 1 1 0 1 1 0 v54' v4+(v3-v4) 2800 / 3450 r54 150 37h 1 1 0 1 1 1 v55' v4+(v3-v4) 2650 / 3450 r55 150 38h 1 1 1 0 0 0 v56' v4+(v3-v4) 2500 / 3450 r56 200 39h 1 1 1 0 0 1 v57' v4+(v3-v4) 2300 / 3450 r57 200 3ah 1 1 1 0 1 0 v58' v4+(v3-v4) 2100 / 3450 r58 250 3bh 1 1 1 0 1 1 v59' v4+(v3-v4) 1850 / 3450 r59 250 3ch 1 1 1 1 0 0 v60' v4+(v3-v4) 1600 / 3450 r60 300 3dh 1 1 1 1 0 1 v61' v4+(v3-v4) 1300 / 3450 r61 500 3eh 1 1 1 1 1 0 v62' v4+(v3-v4) 800 / 3450 r62 800 3fh 1 1 1 1 1 1 v63' v4 output voltage caution there is no connection between v 4 and v 5 terminal in the chip. v 0 ' v 17 ' v 1 ' v 47 ' v 2 ' v 48 ' v 3 ' v 49 ' v 15 ' v 16 ' v 63 ' v 61 ' v 62 ' r 0 r 17 r 1 r 47 r 46 r 2 r 48 r 3 r49 r 14 r 15 r 16 r 60 r 61 r 62 v 4 v 3 v 1 v 0
data sheet s14578ej1v1ds 8 v ss2 + 0.1 v, pol21, pol22 = l data dx5 dx4 dx3 dx2 dx1 dx0 rn resistance ratio 00h 0 0 0 0 0 0 v0" v9 r0 800 01h 0 0 0 0 0 1 v1" v9+(v8-v9) 800 / 8050 r1 750 02h 0 0 0 0 1 0 v2" v9+(v8-v9) 1550 / 8050 r2 700 03h 0 0 0 0 1 1 v3" v9+(v8-v9) 2250 / 8050 r3 650 04h 0 0 0 1 0 0 v4" v9+(v8-v9) 2900 / 8050 r4 600 05h 0 0 0 1 0 1 v5" v9+(v8-v9) 3500 / 8050 r5 550 06h 0 0 0 1 1 0 v6" v9+(v8-v9) 4050 / 8050 r6 550 07h 0 0 0 1 1 1 v7" v9+(v8-v9) 4600 / 8050 r7 500 08h 0 0 1 0 0 0 v8" v9+(v8-v9) 5100 / 8050 r8 500 09h 0 0 1 0 0 1 v9" v9+(v8-v9) 5600 / 8050 r9 400 0ah 0 0 1 0 1 0 v10" v9+(v8-v9) 6000 / 8050 r10 400 0bh 0 0 1 0 1 1 v11" v9+(v8-v9) 6400 / 8050 r11 350 0ch 0 0 1 1 0 0 v12" v9+(v8-v9) 6750 / 8050 r12 350 0dh 0 0 1 1 0 1 v13" v9+(v8-v9) 7100 / 8050 r13 350 0eh 0 0 1 1 1 0 v14" v9+(v8-v9) 7450 / 8050 r14 300 0fh 0 0 1 1 1 1 v15" v9+(v8-v9) 7750 8050 r15 300 10h 0 1 0 0 0 0 v16" v8 r16 300 11h 0 1 0 0 0 1 v17" v8+(v7-v8) 300 / 2750 r17 250 12h 0 1 0 0 1 0 v18" v8+(v7-v8) 550 / 2750 r18 250 13h 0 1 0 0 1 1 v19" v8+(v7-v8) 800 / 2750 r19 250 14h 0 1 0 1 0 0 v20" v8+(v7-v8) 1050 / 2750 r20 200 15h 0 1 0 1 0 1 v21" v8+(v7-v8) 1250 / 2750 r21 200 16h 0 1 0 1 1 0 v22" v8+(v7-v8) 1450 / 2750 r22 200 17h 0 1 0 1 1 1 v23" v8+(v7-v8) 1650 / 2750 r23 150 18h 0 1 1 0 0 0 v24" v8+(v7-v8) 1800 / 2750 r24 150 19h 0 1 1 0 0 1 v25" v8+(v7-v8) 1950 / 2750 r25 150 1ah 0 1 1 0 1 0 v26" v8+(v7-v8) 2100 / 2750 r26 150 1bh 0 1 1 0 1 1 v27" v8+(v7-v8) 2250 / 2750 r27 100 1ch 0 1 1 1 0 0 v28" v8+(v7-v8) 2350 / 2750 r28 100 1dh 0 1 1 1 0 1 v29" v8+(v7-v8) 2450 / 2750 r29 100 1eh 0 1 1 1 1 0 v30" v8+(v7-v8) 2550 / 2750 r30 100 1fh 0 1 1 1 1 1 v31" v8+(v7-v8) 2650 2750 r31 100 20h 1 0 0 0 0 0 v32" v7 r32 100 21h 1 0 0 0 0 1 v33" v7+(v6-v7) 100 / 1600 r33 100 22h 1 0 0 0 1 0 v34" v7+(v6-v7) 200 / 1600 r34 100 23h 1 0 0 0 1 1 v35" v7+(v6-v7) 300 / 1600 r35 100 24h 1 0 0 1 0 0 v36" v7+(v6-v7) 400 / 1600 r36 100 25h 1 0 0 1 0 1 v37" v7+(v6-v7) 500 / 1600 r37 100 26h 1 0 0 1 1 0 v38" v7+(v6-v7) 600 / 1600 r38 100 27h 1 0 0 1 1 1 v39" v7+(v6-v7) 700 / 1600 r39 100 28h 1 0 1 0 0 0 v40" v7+(v6-v7) 800 / 1600 r40 100 29h 1 0 1 0 0 1 v41" v7+(v6-v7) 900 / 1600 r41 100 2ah 1 0 1 0 1 0 v42" v7+(v6-v7) 1000 / 1600 r42 100 2bh 1 0 1 0 1 1 v43" v7+(v6-v7) 1100 / 1600 r43 100 2ch 1 0 1 1 0 0 v44" v7+(v6-v7) 1200 / 1600 r44 100 2dh 1 0 1 1 0 1 v45" v7+(v6-v7) 1300 / 1600 r45 100 2eh 1 0 1 1 1 0 v46" v7+(v6-v7) 1400 / 1600 r46 100 2fh 1 0 1 1 1 1 v47" v7+(v6-v7) 1500 / 1600 r47 100 30h 1 1 0 0 0 0 v48" v6 r48 100 31h 1 1 0 0 0 1 v49" v6+(v5-v6) 100 / 3450 r49 100 32h 1 1 0 0 1 0 v50" v6+(v5-v6) 200 / 3450 r50 100 33h 1 1 0 0 1 1 v51" v6+(v5-v6) 300 / 3450 r51 100 34h 1 1 0 1 0 0 v52" v6+(v5-v6) 400 / 3450 r52 100 35h 1 1 0 1 0 1 v53" v6+(v5-v6) 500 / 3450 r53 150 36h 1 1 0 1 1 0 v54" v6+(v5-v6) 650 / 3450 r54 150 37h 1 1 0 1 1 1 v55" v6+(v5-v6) 800 / 3450 r55 150 38h 1 1 1 0 0 0 v56" v6+(v5-v6) 950 / 3450 r56 200 39h 1 1 1 0 0 1 v57" v6+(v5-v6) 1150 / 3450 r57 200 3ah 1 1 1 0 1 0 v58" v6+(v5-v6) 1350 / 3450 r58 250 3bh 1 1 1 0 1 1 v59" v6+(v5-v6) 1600 / 3450 r59 250 3ch 1 1 1 1 0 0 v60" v6+(v5-v6) 1850 / 3450 r60 300 3dh 1 1 1 1 0 1 v61" v6+(v5-v6) 2150 / 3450 r61 500 3eh 1 1 1 1 1 0 v62" v6+(v5-v6) 2650 / 3450 r62 800 3fh 1 1 1 1 1 1 v63" v5 output volta g e caution there is no connection between v 4 and v 5 terminal in the chip. v 17 '' v 0 '' v 16 '' v 15 '' v 2 '' v 1 '' v 63 '' v 62 '' v 61 '' v 49 '' v 48 '' v 47 '' r 61 r 60 r 59 r 49 r 48 r 47 r 46 v 6 r 62 v 5 r 17 r 0 r 16 r 15 r 14 r 2 r 1 v 9 v 8 v 60 ''
data sheet s14578ej1v1ds 9 data format : 6 bits x 2 rgbs (6 dots) input width : 36 bits (2-pixel data) (1) r,/l = h (right shift) output s 1 s 2 s 3 s 4 ... s 401 s 402 data d 00 to d 05 d 10 to d 15 d 20 to d 25 d 30 to d 35 ... d 40 to d 45 d 50 to d 55 (2) r,/l = l (left shift) output s 1 s 2 s3 s4 ... s 401 s 402 data d 00 to d 05 d 10 to d 15 d 20 to d 25 d 30 to d 35 ... d 40 to d 45 d 50 to d 55 pol s 2n?1 note s 2n note lv 0 to v 4 v 5 to v 9 hv 5 to v 9 v 0 to v 4 note s 2n?1 (odd output), s 2n (even output), n = 1, 2, ...... 201 7. relationship between stb, pol and output waveform the gray-scale voltage is output 4 clocks after the start of d/a conversion in the lsi, in synchronization with the rising edge of stb. during this 4-clock period, hi-z is output. hi-z stb pol s 2n s 2n-1 hi-z hi-z selected voltage v 0 to v 4 selected voltage v 0 to v 4 selected voltage v 0 to v 4 selected voltage v 5 to v 9 selected voltage v 5 to v 9 selected voltage v 5 to v 9
data sheet s14578ej1v1ds 10 c, v ss1 = v ss2 = 0 v) parameter symbol rating unit logic part supply voltage v dd1 ?0.5 to +4.0 v driver part supply voltage v dd2 ?0.5 to +10.0 v logic part input voltage v i1 ?0.5 to v dd1 + 0.5 v driver part input voltage v i2 ?0.5 to v dd2 + 0.5 v logic part output voltage v o1 ?0.5 to v dd1 + 0.5 v driver part output voltage v o2 ?0.5 to v dd2 + 0.5 v operating ambient temperature t a ?20 to +75 c storage temperature t stg ?55 to +125 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended operating range (t a = ?20 to +75c, v ss1 = v ss2 = 0 v) parameter symbol conditions min. typ. max. unit logic part supply voltage v dd1 2.7 3.3 3.6 v driver part supply voltage v dd2 5.225 5.5 5.775 v high-level input voltage v ih 0.7 v dd1 v dd1 v low-level input voltage v il 00.3 v dd1 v v 0 to v 4 0.5 v dd2 v dd2 ? 0.1 v -corrected voltage v 5 to v 9 0.1 0.5 v dd2 v driver part output voltage v o 0.1 v dd2 ? 0.1 v clock frequency f clk 45 mhz
data sheet s14578ej1v1ds 11 c, v dd1 = 2.7 to 3.6 v, v dd2 = 5.5 v 0.275 v, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit input leak current i il 1.0 a high-level output voltage v oh sthr (sthl), i oh = 0 ma v dd1 ? 0.1 v low-level output voltage v ol sthr (sthl), i ol = 0 ma 0.1 v -corrected resistance r v dd2 = 5.5 v v 0 to v 4 = v 5 to v 9 = 2.0 v 6.0 12.0 18.0 k ? i voh v dd2 = 5.5 v, v x = 5.0 v, v out = 4.5 v note1 ?150 ?70 a driver output current i vol v dd2 = 5.5 v, v x = 0.5 v, v out = 1.0 v note1 70 250 a output voltage deviation ? v o t a = 25 c, v ss2 + 1.0 v to v dd2 ? 1.0 v 5 20 mv ? v p?p1 v out = 1.2 to 4.3 v 3 15 mv ? v p?p2 v out = 0.8 to 4.7 v 7 20 mv output swing difference deviation ? v p?p3 v dd1 = 3.3 v v dd2 = 5.5 v t a = 25 c v out = 0.1 to 5.4 v 15 30 mv logic part dynamic current consumption note2,3,4 i dd1 v dd1 1.0 6.0 ma driver part dynamic current consumption note2,4 i dd2 v dd2 , with no load 3.7 7.0 ma notes 1. v x refers to the output voltage of analog output pins s 1 to s 402 . v out refers to the voltage applied to analog output pins s 1 to s 402 . 2. f stb = 48 khz, f clk = 32.5 mhz 3. the typ. values refer to an all black or all white input pattern. the max. value refers to the measured values in the dot checkerboard input pattern. 4. refers to the current consumption per driver when cascades are connected under the assumption of xga single-sided mounting (8 units). switching characteristics (t a = ?20 to +75 c, v dd1 = 2.7 to 3.6 v, v dd2 = 5.5 v 0.275 v, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit start pulse delay time t plh1 c l = 15 pf 9 18 ns t plh2 note 3.8 5.0 s t plh3 note 5.4 8.5 s t phl2 note 3.3 5.0 s driver output delay time t phl3 note c l = 150 pf, r l = 4.7 k ? 4.4 8.5 s c i1 logic input other than sthr (sthl) is t a = 25c 510pf input capacitance c i2 sthr (sthl),t a = 25c 8 15 pf note t plh2 and t phl2 are the time until the voltage reached its target voltage 10% from the falling edge of stb. t plh2 and t phl2 are the time until the voltage reached its target voltage 20 mv from the falling edge of stb. output c l r l = 4.7 k ? c l = 75 pf r l c l measurement point
data sheet s14578ej1v1ds 12 c, v dd1 = 2.7 to 3.6 v, v ss1 = 0 v, t r = t f = 5.0 ns) parameter symbol condition min. typ. max. unit clock pulse width pw clk 22 ns clock pulse high period pw clk(h) 4ns clock pulse low period pw clk(l) 4ns data setup time t setup1 4ns data hold time t hold1 2ns start pulse setup time t setup2 4ns start pulse hold time t hold2 2ns pol21/22 setup time t setup3 2ns pol21/22 hold time t hold3 3ns stb pulse width pw stb 4clk last data timing t ldt 2clk clk-stb time t clk-stb clk stb 4ns stb-clk time t stb-clk stb clk 4ns time between stb and start pulse t stb-sth stb sthr(sthl) 2clk pol-stb time t pol-stb pol or stb 6ns stb-pol time t stb-pol stb pol or 6ns remark unless otherwise specified, the input level is defined to be v ih = 0.7 v dd1 , v il = 0.3 v dd1 .
data sheet s14578ej1v1ds 13 unless otherwise specified, the input level is defined to be v ih = 0.7 v dd1 , v il = 0.3 v dd1 (the clock and display data numbers are examples when the resolution is xga). pw clk(l) clk pol v out stb d n0 to d n5 sthr sthl pw clk(h) t r t setup2 invalid d 1 to d 6 t hold2 12 12 3646566 513 514 t f v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 pw clk t clk-stb t stb-clk t stb-sth t setup1 90% 10% t hold1 t plh1 t pol-stb t stb-pol t plh3 t plh2 t phl2 t phl3 hi-z t ldt pw stb d 7 to d 12 d 1 to d 6 d 7 to d 12 d 373 to d 378 d 379 to d 384 d 385 to d 390 d 3067 to d 3072 invalid invalid v dd1 v ss1 t setup3 t hold3 pol21, pol22 (1st dr.) (1st dr.) invalid 515 519 target voltage + 0.1 v dd2 target voltage + 0.1 v dd2
data sheet s14578ej1v1ds 14 the following conditions must be met for mounting conditions of the pd160903. for more details, refer to the semiconductor device mounting technology manual (c10535e). please consult with our sales offices in case other mounting process is used, or in case the mounting is done under different conditions. pd160903n- xxx : tcp (tab pack age) mounting condition mounting method condition soldering heating tool 300 to 350 c, heating for 2 to 3 seconds : pressure 100g (per solder) thermocompression acf (adhesive conductive film) temporary bonding 70 to 100 c : pressure 3 to 8 kg/cm 2 : time 3 to 5 sec. real bonding 165 to 180 c: pressure 25 to 45 kg/cm 2 : time 30 to 40 sec. (when using the anisotropy conductive film sumizac1003 of sumitomo bakelite,ltd). caution to find out the detailed conditions for mounting the acf part, please contact the acf manufacturing company. be sure to avoid using two or more mounting methods at a time.
data sheet s14578ej1v1ds 15 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd160903 reference documents nec semiconductor device reliability/quality control system (c10983e) quality grades to nec?s semiconductor devices (c11531e) m8e 00. 4 the information in this document is current as of june, 2001. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

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